A known high-density anti-fuse twin-gate isolation (TGI) OTP memory cell realized in 28 nanometer (nm) high-K metal gate (HKMG) complementary metal oxide semiconductor (CMOS) logic process is shown in FIG. 1. Adverting to FIG. 1 (cross-sectional view) the known design includes gates 101 and 103 formed on a p-type well (PW) 105. Each gate 101 and 103 includes a dielectric layer 107, an L-shaped liner 109, and spacers 111. In addition, n+ doped source/drain (S/D) regions 113 and 115 are formed in the substrate 105 adjacent to the gates 101 and a p+ doped S/D region 117 is formed in the substrate 105 between the gates 103. Further, the gates 101 are each utilized as a word line (WL), e.g., WLn and WLn+1, the gates 103 are each utilized as a source line (SL), e.g., SLn and SLn+1, and the n+ doped S/D regions 113 are connected to a bit line (BL) (all not shown for illustrative convenience). The length of the gates 103 needs to be large enough for the p+ implant alignment and the space between the gates 103 needs to be large enough for the p+ doped S/D region 117 to form. However, known challenges to this design include an observed program disturb issue due to potential contour distribution, and reducing the program disturb with a p+ implant results in a larger cell size. A 1 Kbit fin-type field effect transistor (FinFET) dielectric (FIND) resistive random-access memory (RRAM) realized in a 16 nm FinFET CMOS logic process or 16 nm MTP cell is also known. The known MTP cell has a very low set voltage and reset current due to the field enhancement on fin corners; however, a reduction of the cell size is desirable.
A need therefore exists for methodology enabling formation of a compact OTP/MTP cell for high packing density that reduces program disturb/interference and the resulting device.